Editing system for video display terminal

ABSTRACT

A video display terminal is disclosed having an editing system for controlling the entry of characters on the video display as well as the editing or manipulation of the data provided on the display. The editing system is operable between succeeding scan lines of the video display raster. The editing system includes a microprogram function generator which enables the execution of a plurality of steps in an edit by the mere insertion of a single instruction into the video display terminal.

United States Patent Bard July 4, 1972 54] EDITING SYSTEM FOR VIDEO3,396,377 8/1968 Slrout ..340 |72.5 DISPLAY TERMINAL 3,389,404 6/1968Koster ....340/|72.5 3,466,645 9/1969 Granberg el al. ..340/l72.5 1Imam" Bard, phlladelphla, 3,603,966 9/1971 Gregg at al. .,340/l72.5 [73]Assignee; Delta Data Symms Corporation, 3,191,169 6/1965 Shulman et a1...343/5 wells Heights, Pa. I Primary Examiner-Paul 1. Hanan 1 Flledl1970 Assistant Examiner-Mark Edward Nushaum [21] APPLNO': .474AttorneyCaesar,Rivise,Bernstein&C0hen [57] ABSTRACT l i211 iific l 2ff::0 6 f ;7l4 g g fgggg a m 51 55133223;mim ifl [58] Field of Search7340/1725 324'] well as the editing or manipulation of [he data providedan the [56] Rderemes Cited display. The editing systsm is operablebclws'sn succeeding scan lines of the video display raster. The editingsystem in- ITED ST PATENTS cludes a miiroprlogri m fufnction generaqrbwhlfih cnablss the executiono a uran 0 st: s m an e |t t c mere inser-3,SS5,520 1/1971 Helbig et a1 ..340/|72.5 {ion f single E /1 vid di i{firming}, 3,501,746 3/1970 Vosbury ..340/172.5 3,364,473 1/1968 Reitzet a1 ..340/172.5 13 Claims, 10 Drawing Figures 1 6 I02 60 INSTRUCTION STIMING A CURSOR LIM/Ts REGISTER CTRL 46 DEcoDE/i' 5E0 UENCER MIXER 0473470 mm 5 L96 SEQUENCE STATES H4 i C TR- READ/WRITE ran/7km. 75 MCRO FROGmw STARTMEMORICYHE FUNCTION CYCLE .HV/T/ATE e/FROM m 5 ENE RA To tanMEM- 400 [50 1 2:2

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SHEET 5 BF 7 STATE SUBSTATE EN FIG. 7 (ON ITION STATE SUB-STATE EDIT ISTATE sue ST'ATE I EDIT I couor TION l ZOO STATE L J UB STATE I ZOO EDITmake CONDITION J FUNCTION 2 STATE IIZI'III: SUBSTATE 200 I-- MICRO EDITCONDITION I l FUNCTION 3 mcx (ms/1r) CURSOR XCTR l l PRE 551- 05:: x(Le-Fr) I40 ZZLO c Tc TEMP. cuRsoR I g x STOR E 5M0 cry/v5 2/5 /46INVENTOR [RV/N6 GARY BARD Y ZGI/OA/L,M,

A 'T TORNEYS EDITING SYSTEM FOR VIDEO DISPLAY TERMINAL This inventionrelates generally to video display terminals and more particularly to avideo display terminal including an editing system.

The video display terminal has rapidly become a very importantperipheral item for central processing units. The video display terminalenables the visual display of data which will be entered into a computermemory or transmitted to a remote terminal prior to the entering ortransmittal thereof. This means that verification of the data that is tobe inserted into the computer or transmitted is visually available tothe operator of the video display terminal.

Moreover, the video display terminal enables the rapid visual inspectionof data received from a central processing unit. In addition, withvarious improvements that have been provided in video display terminals,formats may be provided on the face of the video display terminal whichenable the rapid entering of data into a data processing system withoutthe necessity of identifying the nature of the information. It has beenfound, however, that video display terminals presently available do nothave adequate editing capability of the data that is presently displayedon the screen of the video display terminal. That is, if a substantialportion of a page of data has been entered onto the screen of a videodisplay terminal and it is desired to edit the information thereon, itis necessary for the operator to enter each character over thecharacters presently in the display until the entire display is correct.

In some cases, this is not only time consuming, but it is alsoimpossible to insert a character or delete a character without requiringa complete destruction of the message. For example, if it is assumedthat ten lines of data appear on the video display terminal and it isfound that a complete line has been omitted between the third and fourthlines on the video display terminal, it would be necessary to completelydelete all of the characters on the fourth through tenth lines of thevideo display terminal. Thus, not only is it necessary to enter the linewhich should be inserted, but the fourth through tenth line must bere-entered below the inserted line.

Re-entering is not only frustrating for the operator, but it is alsotime consuming. Similarly, there are cases where it is necessary toinsert a character on a line and in order to do so, it is necessary todelete each of the characters on the line starting at the position atwhich the character is desired and the succeeding characters on theline. Then, not only is the character entered, but all of the charactersthat have been deleted, re-entered in their proper position.

It is therefore an object of this invention to overcome theaforementioned disadvantages.

Another object of the invention is to provide a new and improved videodisplay terminal which enables immediate access to the refresh memoryfor the video display terminal for editing the contents thereof.

Another object of the invention is to provide a new and improved videodisplay terminal which enables a single instruction to modify aplurality of character locations on the video display terminal.

Yet another object of the invention is to provide a new and improvedediting system for a video display terminal which utilizesmicroprogramming.

Yet another object of the invention is to provide a new and improvedvideo display terminal which utilizes the time between succeeding onesof the horizontal scan lines of the cathode ray tube to carry out theediting instructions.

These and other objects of the invention are achieved by providing in avideo display terminal having input means for receiving data andinstructions and a cathode ray tube for displaying data inserted in theterminal by the input means by providing an alpha-numeric representationof the data on a scan raster which is comprised of a plurality ofparallel scan lines, and an editing means. The editing means isresponsive to the input means and is initiated at the end of the scanline to immediately enter the data and carry out the instructions. Theediting means is operable only during the time between the succeedingscan lines on the cathode ray tube.

Other objects and many of the attendant advantages of this inventionwill be readily appreciated as the same becomes better understood byreference to the following detailed description when considered inconnection with the accompanying drawings wherein:

FIG. I is a perspective view of a video display terminal embodying theinvention;

FIG. 2 is a schematic block diagram of a video display terminal system;

FIG. 3 is a schematic block diagram of the editing control for the videodisplay terminal;

FIG. 4 is a schematic block diagram showing the intercon nection betweenthe instruction register and the edit decoder;

FIG. 5 is a schematic block diagram of the sequencer and the cycle limitdetector;

FIG. 6 is a diagrammatic representation of the signals generated by thesequence clock and the substate clock generator;

FIG. 7 is a schematic block diagram of the microprogram functiongenerator;

FIG. 8 is a schematic block diagram showing the interconnection betweenthe cursor position counter and the temporary storage register for thecursor position;

FIG. 9 is a schematic block diagram of the cursor line counter andtemporary storage register therefor; and

FIG. I0 is a schematic block diagram of the connections to and from theID register and the T register.

Referring now in greater detail to the various figures of the drawingwherein similar references numerals refer to similar parts, a videodisplay terminal embodying the invention is shown generally at 20 inFIG. I.

The video display terminal includes a standard typewriter keyboard 22for entering data on a cathode ray tube display screen 24. Also includedas part of the keyboard 22 are a plurality of instruction buttons orkeys 26 which are utilized to edit the information on the screen 24 aswell as provide instructions for the transfer of the data to and fromthe video display tenninal. A cursor 28 is provided on the video displayterminal to indicate the position that a character entered will beprovided within the field of data illustrated on the screen. The cursor28 is, of course, movable by a plurality of the instruction keys 26 thatare provided on the keyboard so that the position at which data isentered can be controlled.

Referring now to FIG. 2 wherein a schematic block diagram of the videodisplay terminal system is shown. It can be seen that the keyboard 22 isconnected via lines 30 to the circuitry of the video display terminal.Lines 30 are directly connected to the input-output means 34 whichreceives the instructions and the entered characters from the keyboard22. A party line Input-Output (I/O) Bus is also connected to theinput-output means 34 for connection to external devices. Theinput-output means 30 is connected via input and output lines 36 and 38to the edit control 40. Edit control 40 is connected via input andoutput lines 42 and 44, respectively, to a refresh memory 46.

The refresh memory 46 is connected to a character generator 48 whichacts to read out the contents of a read only memory 50. The charactergenerator is connected to the read only memory by input and output lines52 and S4, respectively. A master timing generator 56 is provided forproviding via lines 58, 60 and 62, timing signals for the control of theflow of data throughout the system.

The output of the character generator 48 is connected via line 64 to thecathode ray tube display 24 which displays in alpha-numeric form thecharacters provided to the refresh memory via the input-output device34.

The overall operation of the video display terminal is as follows:

Data and instructions are provided via keyboard 22 to the input-outputmeans 34. The input-output device provides both the data and theinstructions to the edit control 40 via lines 36. The edit controlprovides access via lines 42 to the refresh memory 46 for the insertionof data in the form of character codes to the refresh memory.

The refresh memory is a high speed random access storage unit which ispreferably of the magnetic core type. The refresh memory preferably hasa capacity to store 1,024 eight bit words. Six of the eight bits of eachword are utilized for the code representative of the character which isto be displayed on the cathode ray tube 24. The other two bits of theword are preferably used for the purpose of storing format informationand blink information as well as any information which may be necessaryfor the use of a color terminal.

The edit control 40, thus, operates on the refresh memory to perform allof the entering operations of characters into the storage as well as tomanipulate the data in the refresh memory in accordance withinstructions which are provided by the keyboard 22. The refresh memory46 also acts via the character generator 48 to address various ones ofthe areas of storage in the read only memory 50.

The read only memory is a permanent storage device which includes aplurality of permanently stored character patterns. The read only memoryis programmed to store a pattern of l '"s and "s which represent theshape of each of the standard 64 characters which can be displayed onthe screen. Each character pattern is preferably made up of seven rowsof five bits each. The memory is, thus, broken up into 64 times sevenwords of five bits each. The coded characters in the refresh memory 46are provided in such a code that the code itself acts to address thecharacter patterns associated therewith for generation via the charactergenerator 48 to the display 24.

In the preferred embodiment of the invention, the character generatorprovides from the read only memory 50, the character patterns to thedisplay 24 on a time division basis. That is, the cathode ray tubedisplay utilizes a scan raster which is comprised of a plurality ofhorizontal lines across the screen. Each line is caused by the electronbeam of the cathode ray tube being moved across the screen. Charactersare generated on the screen by blanking and unblanking the cathode raytube beam as it moves laterally across the screen. The beam moves acrossthe screen from left to right and top to bottom until the bottom linehas been completed and then returns to the top of the screen to startanother complete scan.

In the preferred embodiment of this invention, the beam moves across thescreen (262 56) times to create the conventional TV raster scan.Successive sweeps skip every other line creating two fields of scan of262 rt which are equally spaced up and down die screen. This method ofsweeping is known as the interlaced raster scan. In the display of thisinvention, the information on each field is refreshed identically sothat, in effect, only 262 A of the lines on the screen are used ratherthan 525. However, because each field is repeated 60 times per second,the refresh rate for providing the character patterns to the screenassures a flicker-free display. The approximate time for a beam to sweepfrom one side of the screen to the other to form a horizontal line is 52microseconds. The time taken between the righthand side of the beam toreturn to the lefthand side of the screen takes approximately 12microseconds. The cathode ray tube display 24 utilizes standardsynchronization signals for the operation of the scan raster. Thesynchronization signal is mixed with additional data from the charactergenerator 48 to provide the video signal on the display 24.

During the i2 microseconds between each of the lines which are providedon the display, the edit control 40 is utilized to enter data from thekeyboard to the refresh memory 46 and also to reorganize the informationin the refresh memory in accordance with the instructions provided tothe edit control.

The video display terminal is adapted to have a caPacity of 960characters which are grouped into 24 lines of forty characters each.That is, each horizontal line of characters can display forty characterson the display 24 and 24 lines of characters may be displayedsimultaneously.

Each line of characters is comprised of seven horizontal scan rasterlines. That is, since each character pattern is comprised of a matrix offive by seven blanked and unblanked spots, each horizontal scan rasterline includes five points of the character matrix. For example, thefirst line of a scan raster of a character line includes the upper lineof blanked and unblanked portions of the character patterns of each ofthe characters that appear on the line. Similarly, the second, third,fourth, fifth, sixth, and seventh would, respectively, include thesecond, third, fourth, fifth, sixth and seventh line of the characterpattern for each of the characters on the line. By a time divisionbasis, the character generator 48 provides the blanking and unblankingsignals which are utilized on the cathode ray tube beam for providingthe character display. The refresh memory 46 provides the address withinthe read only memory in combination with the timing signal on line 58 inorder to provide the necessary portions of the character matrices as thecharacter pattern is composed onto line 64 and provided to the display24.

Thus, to insert a character from keyboard 22 to the position in thedisplay 24 indicated by the cursor 28, the key associated with thecharacter is pressed. The input data is provided to the input-outputmeans 34 which is then provided via the edit control into the refreshmemory 46. The code representative of the character is, thus, stored atthe position in the refresh memory corresponding to the position on thedisplay 24 at which the cursor 28 is located. Thus, as soon as theraster of the cathode ray tube in display 24 reaches the position atwhich the new character has been entered, the character pattern isaddressed by the refresh memory and the character generator 48 and readfrom the read only memory 50 to provide on line 64, the new characterpattern each time the scan raster line passes through the characterposition.

The edit control 40 automatically increments the control for the cursor28 so that it is moved to the next position to the right on thecharacter display so that the next character inserted by keyboard 22 isautomatically displayed to the right of the previous character inserted.

The edit control system is schematically illustrated in FIG. 3. As bestseen in FIG. 3, the edit control includes an instruction register 70,timing and control unit 72, a decoder 74, a sequencer 76, a microprogramfunction generator 78, a cursor X counter and a cursor Y counter 82, atemporary cursor X store register 84 and a temporary cursor Y storeregister 86, a comparator 88, a T register 90, a limit detector 92, anID register 94 and mixers 96 and 98.

The instruction register 70 is connected to decoder 74 via lines 100.The instruction register 70 also receives signals via lines 102 from thetiming and control unit 72. The timing and control receives signals fromthe master timing unit via line 60 and provides the control signals forenabling the operation of the edit control during the period between thehorizontal lines of the display 24.

The decoder 74 also receives signals via lines 104 from the timing andcontrol unit 72. The decoder 74 decodes the instruction and charactercode to provide an output signal on one of output lines 106. The signalon one of lines 106 provides the microprogram function generator 78 withthe necessary signal to initiate the instruction from the instructionregister 70.

The decoder 74 is connected via line 108 to sequencer 76. Sequencer 76is also connected via input and output lines 110 and H2, respectively,to the timing and control unit 72. The sequencer 76 basically provides asequence of signals which effectively divide the period betweenhorizontal scan lines into sub-intervals or sequence states for carryingout predetermined ones of said microprogram functions which comprise aninstruction from the decoder 74.

The sequence states are provided on sequentially energized ones of lines114 which are connected from the sequencer to the microprogram functiongenerator 78. The microprogram function generator includes a pluralityof output lines which are respectively labeled in accordance with theirfunction. For example, the legend CTRL stands for control and the lineassociated therewith is connected to the mixer 96 to enable the controlof the flow of data to the memory" which refers to the refresh memory.The R/W" legend indicates the signal on the line associated therewitheffectuates a read or write control function to the refresh memory. Thecycle initiate" legend indicates that the signal provided on the lineassociated therewith to the refresh memory starts the memory cycle.

Similarly, the output lines from the microprogram function generatorlabeled 'left," right and "reset" which are connected to the cursor Xcounter effectively indicate that the counter is decremented,incremented and reset, respectively, by the signals on the associatedlines therewith.

The lines connected to the cursor Y counter 82 and having the legendsup, down" and "reset associated therewith are, respectively, decrement,increment and reset lines of the cursor Y counter. The microprogramfunction generator also includes an output line 116 which is connectedto the temporary cursor X store and the temporary cursor Y store andacts to transfer the contents of these stores to the cursor X counterand cursor Y counter, respectively, when a signal is provided on lineII6.

Similarly, a line I18 connected from the microprogram function generator78 to the T register 90 causes the transfer of data into the T register90. Additional output lines are also provided from the microprogramfunction generator to the various components throughout the system whichare seen in greater detail hereinafter with respect to the more detaileddrawings of the connections between various ones of the components ofthe system.

The cursor X counter is connected to the temporary cursor X store 84 viainput and output lines 120 and I22. Similarly, the cursor Y counter isconnected to the temporary cursor Y store 86 via lines I24 and I26.Lines I20 and I24 which are the output lines from the cursor X counterand the cursor Y counter, respectively, are also connected to the mixer98 and, as indicated by the legend Edit Mem. Add. thereon act to accessthe address in the refresh memory at which the contents are altered.

Output lines I24 from cursor Y counter 82 are also connected to thecomparator 88. The temporary cursor Y store register 86 is alsoconnected to comparator 88 via output lines I28.

The T register 90 includes input lines I30 from ID register 94 and lines132 from the refresh memory. The output lines I34 of the T register 90are connected to the mixer 96 which is the input means for and providesthe information to the refresh memory and to the input of the IDregister 94.

The ID register includes, in addition to the input lines from the Tregister 90, input lines 36 from the input-output means 34, line I36which is provided by the microprogram function generator 78 which, whenenergized, acts to transfer the data on lines 36 into the ID register 94and line 138 which is also connected to the microprogram functiongenerator and which provides a signal thereon when the contents of the Tregister 90 are sent to the ID register. It should be noted that thelegendsinput ID"and T ID" represent, respectively,a transfer of datafrom the input source to the ID register and from the T register to theID register. Legends are provided similar to these throughout thedrawings and indicate a flow of data from one register to the other whena signal is provided on that line to the register.

The limit detector 92 includes input lines I40 and I42 which areconnected, respectively, to the cursor X counter and cursor Y counter 80and 82, respectively. The limit detector 92 includes means for comparingthe counts in the counters 80 and 82 with predetermined limits which aredetermined by the number of characters which can be stored on a line andthe number of lines of characters which can be provided on the display.Thus, the limit detector 92 is provided with output lines I44 which areutilized to provide to the timing and control units 72 signals thereonindicative of whether the cursor X counter or the cursor Y counter havea count therein indicative of either the last character position on aline or the last line in the character display. The limit detector 92also provides signals on the output lines 144 to the timing and control72 which are indicative of other limits such as the temporary cursorystore having the same count thereon as that in the cursor Y counter 82.

The mixers 96 and 98 act to provide the buffer storage necessary forinsertion of characters into the refresh memory. Thus, mixer 96 isconnected via output line 148 to the refresh memory and mixer 98 isconnected via output line I50 to the refresh memory. As set forth above,the mixer 96 receives the contents of the T register from lines I34 whenthe microprogram function generator provides a signal on line I18 whichtransfers the contents of the T register to the refresh memory. Themixer 96 also receives input signals on lines I52 from the ID register94.

Referring to FIG. 4, it can be seen that the input lines 36 to theinstruction register 70 are comprised of control lines and eight datalines. The control lines are actuated not only when an instruction isgiven to the video display terminal, but also when data signals areprovided, the control lines have an in struction thereon indicative ofthe fact that a character is to be entered.

The decoder 74 receives the signals from lines and converts the sameinto a I out of N code by providing a signal on one of the edit linesedit I through edit N. Connected to the lines I06 which include theediting signals is an OR gate which is responsive to all of the editlines so that if a signal is provided on any of the edit lines, the ORgate is enabled and provides a signal to flip-flop 162.

The OR gate 160 is connected to the set input of flip-flop 162 via line164. Thus, as indicated by the legend any edit appearing above line I64,any editing signal provides a setting signal for the flop-flop I62. Itshould be noted that the flipflop 162 includes the notation "D adjacentthe input line I64. The legend D in each of the flip-flops shownthroughout the circuitry indicates the set input. The legend CI("indicates that a line connected thereto acts to provide a triggeringfunction for the flip-flop each time a signal is provided on the line.

Line I66 is connected to the clock or trigger input CK of flip-flop I62to effectively cause a change of state in the flipflop in accordancewith the signal provided on line I64. That is, as soon as an instructionis received via lines 36 to the instruction register 70, the decoder 74provides a continuous signal on one of the lines I06 from the decoder.As long as one of the lines I06 remains high, OR gate 160 remainsenabled thereby causing a positive signal to be provided to the setinput of the flip-flop I62.

The flip-flop 162 is not set, however, until such time as the leadingedge of a pulse on line I66 triggers the flip-flop I62 to change itsstate. Thus, if the signal on line I64 is high, it causes the flip-flopto change in state to a 1. If the flip-flop is already in the l state,the flip-flop remains unchanged on the next triggering input signal online I66. The signals on line I66 are provided by the synchronizingclock in the timing and control unit 72 which is responsive to thepulses at the end of each horizontal scan raster line in the videodisplay.

As soon as flip-flop 162 is set, output line I68 thereof goes highthereby enabling the sequencer 76 to be started. The flipflop I62 alsoincludes an input line which is connected to the reset input thereof andcauses the flip-flop to be changed to the 0 state when a flip-flop isprovided thereon.

Referring now to FIG. 5, it can be seen that the sequencer 76 iscomprised of a shift register having eight flip-flop stages which arelabeled, respectively, S0 through S7. Each of the flipflops S0 throughS7 includes a set input (D) and a clock input (CK Stages S4 and S5 ofthe shift register are indicated in phantom since both stages aresimilar and are connected in tandem between S3 and S6 in sequence. Theoutput lines of each of the shift register stages S0 through 87 areconnected to one of the output lines 114 which are connected to themicroprogram function generator.

The output line of each of the shift registers is connected to the setinput of the next succeeding stage of the shift register.

That is, the output of shift register stage S is connected to the setinput of flip-flop S1. The output of flip-flop S1 is connected to theset input of S2 via an OR gate 172. The output of shift register S2 isconnected to the set input of shift register stage S3 and so on through86 which is connected to the set input of shift register S7 via AND gate174. Stages S3 through S6 are connected together as is stage S2 to S3.

The output line of flip-flop S0 is also connected to a first input of ORgate 176. The output of OR gate 176 is connected to line 170 which isconnected to the reset input of flip-flop 162 in FIG. 4. The signal onoutput line 170 indicates that a sequence has been started in the shiftregister which forms the sequencer 76. The output line of flip-flop S0is also connected via line 178 to the set input line of flip-flop 180.The flip-flop 180 also includes a reset input line 182 which isconnected to the output of an OR gate 184. OR gate 184 includes aplurality of inputs from the output of a plurality of AND gates 186.Each of the AND gates 186 is connected at one of its input lines to oneof the edit 1 through edit N lines. Thus, the top AND gate 186 in FIG. 5includes a line which is connected to edit 1, the next AND gate 186includes an input line from edit 2 and so on through the lowermost ANDgate 186 which includes an input from the edit N line.

Each of the instructions has limits incorporated therein which end thesequencing function of the shift register 76 to initiate various ones ofthe microprograms. That is, each of the main instructions normallyutilizes a plurality of complete cycles of the sequence shift register76. However, when a predetermined condition has been reached, the limitsare detected and provide signals to AND gates 186 to indicate that aparticular editing instruction has been substantially completed. Thus, ahigh signal will be provided on each of the lines to the AND gates 186associated with the particular instruction. The line associated with thelegend state" indicates the portion of the sequence in which theselimits are detected. That is, each of the microprogram functions arecarried out in predetermined portions of a cycle.

Thus, if a test is made of the status of the circuitry to determine theend of the instruction associated with the edit 1 signal during the S2state of the sequencing cycle, the line of lines 114 connected to theoutput of flip-flop S2 is connected to the topmost AND gate 186 in FIG.5.

Thus, if any of the AND gates 186 is enabled by a high signal on each ofits input lines, the OR gate 184 receives an enabling signal whichcauses the output line to reset the recycle flip-flop 180. When theflip-flop 180 is in the set state, a high signal is provided on outputline 188 which is labeled the recycle signal. When the flip-flop 180 isreset, the signal on output line 190 is made high thereby indicatingthat there should not be a recycle as evidenced by the legend recycle"having a bar, or the logical not sign, over the top thereof.

The OR gate 172 also includes an input from the output of AND gate 192.The AND gate 192 includes a first input from line 188 of flipflop 180and a second input line 166 which receives the signal from thesynchronizing clock which provides the signal at the end of each of thehorizontal scan lines on the cathode ray tube display. Line 188 is alsoconnected to the second input of OR gate 176 and prevents the sequenceflip-flop 162 (FIG. 4) from being set again during an instruction edit.

The output line 190 of flip-flop 180 which is labeled recycle isconnected to the second input of AND gate 174 which is connected betweenstages S6 and S7 of the shift register 76 of the sequencer. To each ofthe clock inputs of the flip-flop stages S0 and S7 of the shift register76 is connected input line 192.

Line 192 receives the signals from the output of the sequence clockwhich is provided in the timing and control unit 72. The sequencingclock line 192 is also connected to a substate clock generator 194 whichprovides, on the output of lines 196 and 198, signals CKA and CKB,respectively. These output signals are illustrated in FIG. 6. [t can beseen that the sequence clock signal is a square wave pulse. in responseto the sequence clock signal, the substate clock generator generatesclock signals CKA and CKB which act effectively to divide the sequencestate into two substates and B, respectively.

The sequence clock enables the set state of flip-flop 162 in FIG. 4 tocause a l to be shifted through the stages S0 through 87 of the shiftregister 76. That is, when the flip-flop 162 is set, a 1 signal isprovided on line 168 to the set input of shift register stage S0. Thefirst clock pulse from the sequence clock on line 192 causes the shiftregister stage S0 to be changed to the 1 state in accordance with the lsignal provided on line 168. As soon as the shift register stage S0becomes a l, the output line thereof goes high thereby causing the ORgate 176 to be enabled and causing line 170 to reset the flip-flop 162.Thus, the output line of the flip-flop 162 goes low thereby causing theinput line 168 to flip-flop stage S0 to go low. Accordingly, on the nextclock pulse, flip-flop S0 is switched to the 0 state but because theoutput line of S0 had been high on the same clock pulse, flip-flop S1 ischanged from the D to the 1 state. On the next clock pulse, the 1 inflip-flop S1 is shifted to the flip-flop S2 via OR age 172. Upon thenext succeeding clock pulses, the l is shifted from the stages S2through S6. If AND gate 174 is enabled by a high signal on line 190, thenext pulse causes the l to be shifted into S7. Otherwise, the l is lost.It should be noted that after the I has been shifted out, a 0 has beenplaced in each of the flip-flop stages due to the fact that the passedstages are in the 0 state.

As soon as the flip-flop S0 was changed in state to the 0 state, theoutput line thereof caused the flip-flop to be set to cause a highsignal on output line 188 which indicated that a recycle of the shiftregister should take place unless during the shifting of the 1 throughto shift register stage S6, the flipflop 180 was not reset by theoccurrence of a condition during one of the states S1 through S6. If theflip-flop 180 is not reset prior to the shifting of the l into flip-flopS6, the l is lost dur ing the next sequence clock pulse because of thefact that the AND gate 174 cannot be enabled since the recycle inputline 190 is at a low potential and the AND gate 174 is not enabled bythe setting of flip-flop 7. The l is thus shifted out of the shiftregister 76. The editing system is then inactive until the nextsynchronizing clock pulse is provided at the end of the next horizontalscan raster line. As soon as the next horizontal scan raster line iscompleted, the synchronizing clock signal is provided on line 166 to ANDgate 192 which thereby causes gate 192 to be enabled since the recycleline 188 is high. A l is then inserted in flip-flop S2 upon the nextsequence clock pulse. The 1 is then shifted from shift register stage S2through S6 with the flip-flop 180 remaining in the set state unless alimit has been reached indicating that there should not be a recycle.When the limit has been reached during states S2 through S6, theflip-flop 180 is reset thereby causing gate 174 to be enabled with theflip-flop S6 is set. This causes the 1 to be shifted from the flip-flopS6 to flip-flop S7 which causes the output line of the flip-flop S7 toinitiate the termination of an instruction.

The microprogram function generator is shown schematically in FIG. 7.The microprogram function generator basically comprises a plurality ofgates 200, each of which is logically connected to produce an outputsignal when a specific microfunction is to be carried out. Each of thegates 200 includes a plurality of AND gates 202, the output of which areeach connected to the input of an OR gate 204.

Where no predetermined condition is required for a microfunction to becarried out, the AND gate 202 would not have a condition input. Forexample, if microfunction 1 enables the setting of the temporary cursorstorage registers 84 and 86 to the present contents of the counters 80and 82, the condition input'to the AND gates 202 is not necessary.Accordingly, each instruction that uses this microfunction 1 has an ANDgate 202 provided in gate 200 therefor. In addition, the state andsubstate lines connected to the inputs of AND gates 202 are connected tothe outputs of the sequence shift registers 76 in accordance with thestate and substate of the sequence at which the microfunction should becarried out. Accordingly, if in the instruction associated with edit 1,the microfunction l is to be carried out during the time that theflip-flop S1 is in the 1 state, and during substate A thereof, the stateline to AND gate 202 is connected to the output of flipflop 81, thesubstate line is connected to the CKA line and the edit line isconnected to the edit 1 line of lines 106. Thus, if each of the lines ishigh, the AND gate 202 causes the microfunction 1 output line to behigh. Thus, it can be seen that the AND gates 202 are provided for eachof the conditions that require a specific microfunction to be carriedout. An OR gate is provided at the output of the AND gates so that anyone of these conditions satisfies the requisite for carrying out thefunction. Similarly, in each of the other gates 200 for the othermicrofunctions that are to be carried out, AND gates 202 are provided inaccordance with the number of conditions which require the execution ofthe microfunction.

In FIG. 8, the connection between the cursor X counter and the temporarycursor store is shown. The cursor X counter 80 includes a first inputline ([NCX) from the microprogram function generator which incrementsthe counter and thereby effectively changes the position of the cursorby moving it to the right. similarly, the line 212 (DECX) from themicroprogram function generator enables the cursor X counter to bedecremented which effectively means that the position of the cursor ismoved to the left on the display. Line 214 (RESET) from the microprogramfunction generator 78 enables a signal thereon to reset the counterwhich effectively puts the cursor at the start of the line.

Line 216 (TC C) is connected to the preset input of cursor X counter 80and effectively causes the contents of the temporary cursor storageregister 84 to be placed into the cursor X counter 80. Line 218 (C TC)from the microfunction generator to the temporary cursor X store 84effectively causes the transfer of the contents of the cursor X counterto the temporary cursor X store.

Each of the stages of the cursor X counter 80 and the temporary cursor Xstorage register 84 are connected to each other via lines 120 and 122 sothat the contents in either of the registers can be preset in the otherregister.

Lines 140 which extend to the limit detector 92 are connected to theoutput lines 120 of the cursor X counter. 80. The limit detector 92includes coincidence gates for each of the limits that it is to detect.For example, to determine the end of a line, the gating is so connectedto lines 140 that only the code representative of the last character ina line can enable the gate 220 provided in the limit detector whichindicates the end of a line. For example, if 40 characters can be storedon a line, the coded representation of the number 40 is detected (wherethe positions are numbered one through 40) by the AND gate 220 whichprovides an enabling signal on the output line 144 to indicate that thecursor is at the end of a line as indicated by the contents of thecursor counter.

The connection between the cursor Y counter and the temporary cursor Ystorage 86 is illustrated in FIG. 9. The input lines to the cursor Ycounter 82 include line 222 (INCY) from the microprogram functiongenerator which enables an incrementing by one of the cursor Y countereach time a pulse is received on line 222. This effectively causes theposition of the cursor to be moved down on the display.

Similarly, line 224 (DECY) from the microprogram function generatorenables a signal thereon to decrement the Y counter which effectivelycauses the cursor to be moved upwardly on the display. A signal on inputline 226 (RESET) to the cursor Y counter causes the counter to be resetwhich effectively causes the cursor to be moved to the top line.

Counter 82 also includes an input line 228 which is connected to theoutput of OR GATE 230. The OR gate 230 has two inputs, one of which isconnected to line 116 from the microprogram function generator whichenables the contents of the temporary cursor Y store 86 to be presetinto the cursor Y counter 82. The second input line 232 to the OR gate230 is connected to the microprogram function generator 78 to enable thetransfer of the code for the last line of characters to be inserted intothe cursor Y counter 82.

Each of the output lines of the stages of the cursor Y counter 82 areconnected via lines 124 to the input of the stages of the temporarycursor Y store 86. The output lines of the temporary cursor Y store areconnected via lines 126 to a plurality of AND gates 234. Connected tothe input of each of the stages of the cursor Y counter 82 are OR gates236. Each of the OR gates 236 has one input connected to the output ofAND gate 234 from the stage associated therewith of the temporary cursorY store 86.

Output line 238 (TC C) from the microfunction genera tor is utilized toenable the contents of the temporary cursor Y store 86 to be preset inthe cursor Y counter 82. Line 238 is connected to the second input ofeach of the AND gates 234. Thus, each time line 238 is enabled by themicroprogram function generator 78, AND gates 234 are enabled in ac'cordance with the contents of the temporary cursor Y store to preset thecursor Y counter 82.

The second input line of each of the OR gates 236 is connected to theoutput of a plurality of AND gates 240. The AND gates 240 are connectedto positive voltage and ground in accordance with the code for the lastline of the display. That is, since the display has a capacity of 24lines, the binary code for 24 is connected via AND gates 240 to OR gates236 so that a pulse on line 232 causes the cursor Y counter to be presetto the count for the last line thereby setting the cursor into the lastline on the display.

It should be understood that although only the gates and inputs forthree stages of the cursor X and Y counters are shown herein forpurposes of clarity, each of the counters and 82 and the storageregisters 84 and 86 preferably include six stages. The remaining stagesare, of course, connected in the same manner as are the three stagesshown in FIGS 8 and 9.

The output lines 124 of the cursor Y counter 82 are connected via lines142 to the limit detector 92 which includes gating 242 which is adaptedto be enabled if the counter has a count equal to the number of the lastline of the display. Thus, in the preferred embodiment, when the code onlines 142 is equal to the decimal number twenty-four, an output signalis provided on one of the lines 146 indicative of the fact that the lastline is in the cursor Y counter.

Lines 142 are also connected to a comparator 244 which is provided inthe limit detector. Also connected to the comparator 244 via lines 144are the output lines 126 of the temporary cursor Y store 86. When thecode on lines 144 is similar to the code on lines 142, the comparator244 indicates that this condition is so by providing an enabling signalon one of lines 146 to indicate that the contents of the temporarycursor Y storage is equal to the contents of the cursor Y counter.

The transfer of data into and out of the T register and the 1D registeris shown schematically in FIG. 10. Both the 1D register 94 and the Tregister preferably comprise eight flip-flop stages for storage of thecoded word. The inputs to each of the stages are, respectively, entitleddata 1 input data n input. Similarly, the T register 90 has each of itsinputs labeled "data 1 input" through data n input." The input labeled"CK" in both the ID and T registers indicates that it enables the stagesof the register to be changed in accordance with the input provided tothe set input of each of the flip-flops.

A plurality of the OR gates 250, one for each of the data inputs to 1Dregister 94, are provided. Each of the OR gates is connected to one ofthe inputs of the 1D register. Each of the OR gates 250 is connected tothe outputs of AND gates 252. One of each group of three AND gates isconnected to the output of one stage of the T register 90. One of theAND gates of each of the groups of three AND gates is connected to oneof the input lines 36 of the data input and the third one of each of thegroup of three AND gates is connected to one of the output lines fromthe refresh memory.

The input lines from the output of the T register 90 are, respectively,labeled Tl Tn, the input data lines are labeled 1N1 lNn, and the refreshmemory lines are labeled RM] RMn, respectively.

Each of the AND gates 252 is a two input AND gate. Line 138 (T- ID) isconnected to the other input of the AND gates which are connected to theoutput of the T register. Line 138 is connected to the microprogramfunction generator and enables the transfer of the contents of the Tregister to the ID register. Line 136 (INPUT DATA ID) from themicrofunction generator is connected to each of the AND gates which areconnected to the lines 36. Line I36 enables the microprogram functiongenerator to transfer the input data to the ID register 94.

Line 254 (RM ID) is connected to the other input of each of the ANDgates which are connected to the output of the refresh memory. Line 254is also connected to the microprogram function generator and enables themicroprogram function generator to transfer the contents of theaddressed location of the refresh memory to the ID register.

An OR gate 256 is also provided, the inputs of which are connected tolines 136, I38 and 254. The output of OR gate 256 is connected to thetrigger input (CK) of the ID register so that a pulse on either of lines136, 138 or 254 enables ID register 94 to store the inputs provided onthe data 1 through data n input line.

The output lines of each of the stages of ID register 94 are,respectively, labeled IDI through lDn. Each of these lines are connectedto one input of one of a plurality of AND gates 258. The output linesfrom each of the stages of the T register 90 are, respectively, labeledTI through Tn. Each of these output lines are connected to one of aplurality of AND gates 260. A plurality of OR gates 262 are provided,each of which is connected to the output of one AND gate from the group258 and one AND gate from group 260 which is associated with one stageof each of the registers. That is, the AND gates 258 and 260 which areassociated with the first stage of the ID register and the T registerare connected to a first one of the OR gates 262 and so on through tothe AND gate 258 which is associated with the in stage 94 and AND gate260 which is as sociated with the n stage of T register 90 which areconnected to the nth OR gate 262.

The output of the OR gates 262 are connected to the first through nthbits of the input register in the refresh memory. The contents of theinput register of the refresh memory are then stored at the locationspecified in the cursor X and cursor Y counters 80 and 82. The IDregister contents are transferred to the refresh memory when a pulse isprovided on line 264 (ID RM) which is connected to the other input ofeach of the AND gates 258. Line 264 is connected to the output of themicroprogram function generator 78 and acts to transfer the contents ofthe ID register to the refresh memory when an enabling signal isprovided thereon. Similarly, line 266 (T RM) is connected to each of thesecond inputs of the AND gates 260 and is also connected to themicroprogram function generator which provides an enabling signal totransfer the contents of the T register to the refresh memory.

Connected to each of the data I through data n inputs of the T register90 are a plurality of OR gates 268. One OR gate is provided for each ofthe inputs to the T register. Each OR gate is connected to the outputsof a plurality of AND gates 270. One input of one of the AND gates ofeach of the pairs of AND gates 270 is connected to one of the outputlines of the ID register 94. One input of the other of the pairs of ANDgates is connected to the output lines of the refresh memory. Line 272(ID T) which is connected from the microprogram function generator isconnected to each of the AND gates associated with the output line fromthe ID register 94. A signal on line 272 enables the transfer of thecontents of the ID register to the T register. Line 274 (RM T) isconnected to each of the AND gates which are connected to the outputs ofthe refresh memory. Line 274 is also connected from the microprogramfunction generator and an enabling signal thereon causes the transfer ofthe refresh memory location at the address of the cursor to betransferred to the T register 90. Lines 272 and 274 are connected to theinputs of an OR gate 276, the output of which is connected to thetrigger input of the T register 90. Thus, when an enabling signal isprovided on either line 272 or 274, the T register is triggered to beset to the input provided on the output lines of the OR gates 268.

As seen hereinabove, the combination of the editing instruction providedby the instruction register to the decoder and in turn to themicroprogram function generator and the sequence states provided by thesequencer 76 to micropro' gram function generator cause variousrnicrofunctions to carry out a complete instruction. The following is amicrofunction table broken down into the areas of control, namely, thememory control, the cursor control and miscellaneous control with anabbreviation of the function to the right thereof:

MICROFUNCTION TABLE MEMORY CONTROL ABBREVIATIONS Start memory cycle CYINSelect either a read READ or WRITE cycle or a write cycle Transfer datain memory RM-'T to the T register Transfer data in memory RM lD to IDregister Preset the memory input to the lD RM contents of the IDregister Preset the memory input to the T-'RM contents of the T registerCURSOR CONTROL Reset cursor X counter RCX (start of line) Reset cursor Ycounter RCY (top line) Preset cursor Y counter PCY (bottom line)Increment cursor X counter INCX (move to right) Decrement cursor Xcounter DECX (move to left) Increment cursor Y counter INCY (move cursordown) Decrement cursor Y counter DECY (move cursor up) Preset the cursorX counter TC- C and cursor Y counter with the contents of the temporarycursor X store and Y store registers, respectively Preset the temporarycursor X C-TC storage register and the Y storage register to the presetcount in the cursor counter and cursor Y counter MISCELLANEOUS CONTROLTransfer the contents of the T T- lD register to the ID registerTransfer the contents of the ID -T ID register to the T register Insertcode for blank space BLANK- T in T register Insert code for blank spaceBLANK-1D in ID register Reset instruction register in- END EDIT cludingstage associated with the instruction Each of the instructions which canbe initiated by pressing one of the keys on keyboard 22 is comprised ofa plurality of the above rnicrofunctions and each of thesernicrofunctions are carried out in the intervals between horizontal scanlines on the cathode ray tube display 24.

In addition to the keys for moving the cursor location on the screen andthe keys for the transfer of data, the following instruction keys areincluded on the keyboard with the function thereof listed on the right:

INSTRUCTION TABLE KEY FUNCTION Clears the entire line from the cursor tothe end of the line on the cathode ray tube screen.

Clears the screen from the cursor position to an end of message symbol lClears the screen completely and causes the cursor to be put in the toplefthand position of the screen (home position).

Places a blank at the cursor position on the screen and moves all of thecharacters from the cursor position to the end of the line to the rightby one position.

Deletes the character at the cursor position and causes each of thecharacters to the right of the deleted character to the end of the lineto be moved one position to the left.

Moves all of the lines from the cursor line down one line from thecursor. The cursor line is left blank.

Deletes the line in which the cursor is located and moves all of thelines below the cursor up one line.

Places a new character at the location of the cursor (this instructionis carried out each time a new character is pressed on the keyboard 21).

Clear Line Clear Message Clear Page Insert Character Delete CharacterInsert Line Delete Line Enter Each of the above instructions is carriedout by a plurality of the hereinabove specified microfunctions. In orderto examine the operation of the edit control during the aforementionedinstruction, it will be assumed that the display 24 has a capacity ofonly four lines of four characters. Thus, the fourth character in eachline would be the last character in the line and the fourth line wouldbe the last line on the display. In the examples hereinafter described,the positions will be denoted by the coordinates of the position on thescreen. For example, the character in the first or top line and at thefirst or leftmost position on the line will be designated as being inposition I 1. Similarly, if a character position for the location of thethird line, second character position is denoted, the designation wouldbe 3-2.

In Chart l hereinbelow, the Clear Line" instruction is shown prior toexecution and after execution.

It can be seen that the display prior to Clear Line instruction has thecharacters A," B, "C" and D" in the first line and "E," F, G, "H" in thesecond line, I," J," l," L" in the third line and M, "N," "O," P in thefourth line. The character "T" represents the end of message characterand the line underneath the character F" in the second line, secondcharacter position (2-2) represents the position of the cursor. Thus,the cursor is in the position on the screen at which the character F" islocated.

The Clear Line instruction is carried out by the followingmicrofunctions during the sequence states associated therewith:

SEOU ENCE STATE MICROFUNCTION S0 C-TC SI SET RECYCLE 54B BLANK-T TEST(Does C 4) S5 TRM 55B WRITE S6 INCX IfC 4, proceed to S7, otherwiserecycle S7 TC+C END EDIT The sequence of the microfunctions above isbest un derstood by referring to FIG. 3 wherein it can be seen that theinstruction register 70 receives the Clear Line instruction when theClear Line instruction key is pressed on the keyboard 22. This causesthe decoder 74 to provide a positive signal on the edit line 106 whichcorresponds to the Clear Line instruction. The line 106 whichcorresponds to the Clear Line instruction stays high until such time asthe Clear Line instruction has been completely executed and theinstruction register reset.

Referring now to FIG. 4, it can be seen that OR gate I60 is enabled bythe high signal on one of the lines 106 thereby causing flip-flop 162 tobe set as soon as the next horizontal line of the scan raster of videodisplay 22 is ended. Upon the reception by the sequence shift register76 of the next sequence clock pulse a l is placed in stage S0 of theshift register. During the time that flip-flop S0 is set, one of thegates 200 in FIG. 7 of the microprograrn function generator is enabledas a result of the high signal on the output line of flip-flop S0, thereception of the clock pulse CKA and the signal on the edit line I06corresponding to the Clear Line instruction which causes the executionof the microfunction C TC.

As set forth above, this microfunction causes the position of the cursorwhich is recorded in the cursor X and cursor Y counters to be recordedin the temporary cursor X store and Y store 84 and 86, respectively.Upon the next sequence clock pulse, the I in stage S0 is shifted toflip-flop stage 81.

As the 1" is shifted out of shift register stage St), the recycleflip-flop 180 is set thereby causing the signal on the recycle line 188to go high. The l is then shifted during the next three clock pulsesfrom shift register stage 81 to S4. During the period that the 1 is inshift register stages S2 and S3, no further rnicrofunctions take place.During the period that the l is in shift register stage S4 and duringthe high portion of the clock pulse CKB, the T register is set to a coderepresentative of a blank (BLANK T). Also during the time that a l is inshift register stage S4, one of the gates 186 (FIG. 5) which isconnected to the output of the gate 220 (FIG. 8) of the limit detector92 is enabled if the code for the last line position or the end of theline is detected. That is, in the preferred embodi' ment of the system,40 characters are provided on a line. Accordingly, since the charactersare numbered 0 to 39, if the code 39 is provided to gate 220, then alimit signal would be provided to one of the gates 186, which is alsoresponsive to the fourth stage of the shift register 76, and the editline corresponding to the Clear Line instruction which would enable thegate I86. However, if the limit is not reached, in other words, in thisexample, if the cursor X counter is not at 4, the gate 186 associatedwith this microfunction is not enabled and the recycle flip-flop is notreset.

Accordingly, line 188 of the flip-flop I80 remains at a high voltagelevel. when the l in shift register stage S4 is shifted to stage S5, themicrofunction T RM is carried out which effectively puts a blank code inthe input register to the refresh memory.

When the clock pulse B goes high during the period that the I is in theflip-flop stage $5, the Write" instruction is emitted by themicroprogram function generator 78 and causes the blank to be writteninto the location in the refresh memory 22. Accordingly, the screen goesblank at the position 2-2 at which the character F was originally shown.When the sixth clock pulse causes the l to be shifted from S5 to S6, thefunction INCX is carried out which causes the cursor X counter 80 to beincremented and thus moves the cursor to the position 2-3. The seventhclock pulse does not cause the l in flip-flop stage S6 to be shiftedinto flip-flop 87 because of the fact that AND gate 174 cannot beenabled due to the recycle line 190 remaining low in potential. The l isthen shifted out of the sequence register 76 and the edit controlremains inoperative until the end of the next horizontal scan rasterline.

At the end of the next horizontal scan raster line, the synchronizingclock pulse is again provided on lines I66 to flip-flops I62 and ANDgate I92. (FIGS. 4 and 5) The trigger input to flip-flop 162 does notchange the state of flip-flop 162 because the line 170 to the resetremains high thereby inhibiting the flip-flop from being switched to theset state as long as the recycle line 188 to OR gate 176 remains high.

However, the synchronizing clock pulse to line 166 to the AND gate 192causes the flip-flop S2 of the shift register 76 to be set upon the nextsequence clock pulse. This effectively puts a 1 in shift register stageS2. Thus, the sequence states S and S1 are eliminated from the nextcycle of the sequence since the l is already in state S2 where it isshifted from S2 through S6. The microfucntions which were executedduring the first sequence of the sequencer shift register 76 is thusrepeated with the exception of the microfunctions which are initiatedduring the sequences of S0 and SI. Thus, when the l is shifted into theflip-flop stage S4, a blank code is again set into the T register 90(BLANK T). Also, during the sequence S4, the limit AND gates 186 areenabled to test whether the cursor X counter has the end of line codetherein as determined by the gate 220 of the limit detector 92. Sincethe X counter 80 was set to 3 during the previous sequence, the test fora 4 in the cursor X counter 80 fails. Accordingly, flip-flop I80 remainsin the set state causing the recycle line I88 to remain high.

During the sequence state S5, the code for a blank space in the Tregister is transferred to the input means for the refresh memory.During the substate B of the S5 state of the sequencer, the Riteinstruction is provided by the microprogram function generator to causethe blank space to be written into the portion of the refresh memorywhich formerly stored the character code for the letter "C." Thus, thescreen is blank where the G formerly was displayed.

During the sequence state S6, the cursor X counter 80 is againincremented by the microprogram function generator 78 causing the cursorX counter to be incremented to the number 4. The cursor Y counterremains at 2.

Thus, it can be seen that the first two sequences of the sequence shiftregister 76 cause first the F to be blank and then the G to be blank. Itshould also be noted that since the recycle line 190 remains low, thenext clock pulse causes the l in the shift register stage S6 to beshifted out thereby ending the operation of the edit control until theend of the next horizontal scan raster line.

As soon as the next horizontal scan raster line is completed, thesynchronizing clock I66 again causes gate 192 to be enabled which inturn causes the shift register stage S2 to be set to the I state. Thus,in the next sequence states S2 through S6, the H in line 2 of thedisplay is set to blank. However, during state S4B, the test for the 4in the cursor X counter, causes the enablement of one of the gates 186which causes the flip-flop 180 to be reset and thereby cause the outputline 190 to go high thereby causing AND gate 174 to be enabled. Thus,after the 1 is in flip-flop state S6, the next sequence clock causes theI to be shifted into flipflop stage S7. During sequence state S7, thecursor X counter and cursor Y counter are preset to the count presentlyin the temporary cursor X store and Y store 84 and 86, respectively.Also, a signal is provided from the microprogram function generator tothe instruction register 70 which is reset thereby ending the editingsignal from the decoder 74 on one of the lines 106.

It should be noted that since in the preferred embodiment of thisinvention, the characters that are displayed on each line of the displayis 40, the recycle sequences would have continued until a 39 had beenplaced in the cursor X counter 80. Even though the character positions 4through 39 were blank, the editing instruction continues to the end ofthe line. This entire operation is completed during the retrace timesbetween each of the horizontal lines on the video scan raster. It can,therefore, be seen that the entire instruction is executed in less timethan is required to complete one video scan raster.

When the "Clear Page instruction is provided by pressing the Clear Pageinstruction key in the keyboard 22, the entire screen is made blank. Thefollowing is a schematic description of the operation of the editingcontrol during the sequences S0 through S7. Where a sequence has beenleft out, it will be assumed that no editing microfunctions have takenplace during the sequence state:

SEQUENCE MICRO- DESCRIPTION STATE FUNCTION S0 RCX, RCY Resets the cursorX and Y counters to [-1. SI SET Recycle flip-flop I is RECYCLE setmaking output line I88 high.

The code for a blank space is placed in T register as in "Clear Line"instruction.

A test to see ifCX equals "4" and CY equals "4. (The end ofline and lastline counts and therefore the last position on the screen.)

The contents of the T register are then transferred to the input of therefresh memory.

The contents of the input to memory are placed in the position set intothe position addressed by the cursor and cursor Y counters. The cursor Xcounter is incremented.

TEST

SSB WRITE S6 INCX END EDIT It can be seen from the above sequence thatduring the first sequence of the shift register 76, the cursor X and Ycounters are set to the position ll. During state SI, the flip-flop isset to cause output line I88 to go high. During state S48, the charactercode for a blank is put in the T register and the test is made todetermine whether the counters 80 and 82 have the end of line and lastline codes therein. If they do not, the sequence will be recycledstarting with a I placed in sequence state 82 and thus only the statesS48 through S6 will be repeated. If, however, the recycle is initiatedby reason of a 4 being in each of the cursor X and cursor Y counters,then a recycling will not take place and rather state S7 is enabledwhich causes the end of the edit.

It should be noted that the cursor X counter recycles after the lastcharacter position on a line. That is, if position 4 is the highestposition that the cursor X counter counts to, it recycles to l andcauses a carry to be put into the cursor Y counter which automaticallyincrements the cursor Y counter. Thus, after the position 1-4 has beenplaced in the cursor counters, an incrementing of the cursor X countercauses the count in the cursor counters to be 2-] and so on until thecount reaches 4-4 at which time the recycle flip-flop I80 is reset tocause the end of the cycle.

It can, therefore, be seen that in each of the sequences of the ClearPage instruction, one of the character spaces is blanked in the order ofleft to right and then down through the next line. At the end of theedit instruction, the cursor counter is reset to cause the cursor to beput in the home position in the upper left hand corner of the screen.

The Clear Message instruction clears the screen from the cursor positionto the end of message symbol. Chart II which is provided hereinbelowillustrates the display prior to instruction and the display after theClear Message instruction has been executed.

CHART II CLEAR MESSAGE INSTRUCTION A B C D A B C D E F G H E DisplayPrior to Display After Instruction Instruction Executed The ClearMessage instruction is carried out in exactly the same sequence as theClear Line instruction with the exception that in the state and substate84B, the test in the Clear Message is made to determine whether the endof message character is located at the position in the refresh memory atwhich the cursor counter is presently addressing. As soon as the end ofmessage character t is reached, the recycle flip-flop is reset therebypreventing further recycling and termination of the Clear Messageinstruction.

The "Insert Character" instruction causes a blank space to be insertedat the position of the cursor with each of the characters from thecursor to the right of the line moved one position to the right. Thisinstruction is best understood in connection with Chart III hereinbelowwhich shows the display prior to the Insert Character instruction andthe display after the Insert Character instniction has been executed.

CHART III INSERT CHARACTER INSTRUCTION A B C D A B C D I] l L I] l LDisplay Prior to Display After Instruction Instruction Executed Itshould be noted that the H which is originally at the end of the line islost due to the fact that there are no more character positionsremaining after the fourth position on the second line. In the preferredembodiment where the display includes 40 character positions, thecharacter H is located to the right of the G as illustrated after theinstruction is executed.

The sequence of operations in the Insert Character instrucset.

A memory cycle is started whereby the address of the refresh memorydesignated by the count in the cursor X and cursor Y counter isaccessed.

The contents of the addressed portion of the refresh memory aretransferred to the T register.

The cursor X counter is checked to determine whether the cursor is atthe end of the line.

The contents of the ID register is provided to the input of the refreshmemory. The blank code which has just been transferred from the IDregister is written into the location of the refresh memory at which thecursor X and Y counters are positioned.

The cursor X counter is in' cremented.

The contents of the T register are preset into the ID register.

RECYCLE 83 READ TEST S5 ID RM S58 WRITE 86A INCX 86B T-'ID If during thetest, it is determined that the .cursor X counter indicates the end ofthe line, proceed to S7, otherwise recycle S7 TC-C The contents of thetemporary cursor X and Y store are preset into the cursor X and cursor Ycounters,

In order to carry out the Insert Character instruction on the displayshown in Chart III prior to the Insert Character instruction, thefollowing events occur: During the first sequence, the cursor address 22is stored in the temporary cursor store. The ID register is set to theblank code and the recycle flip-flop set. The character F at theposition 2-2 in the refresh memory is then transferred to the Tregister. A test is made to determine whether the end of line code is inthe cursor X counter. Since it is not, the recycle flip-flop remainsset. The contents of the ID register which is the code for a blank isthen sent to the memory position 2-2 causing a blank to appear where theF formerly appeared. The cursor X counter is then incremented causingthe cursor address to be 2-3. The F in the T register is thentransferred to the ID register.

During the second sequence, the operations taking place during states S0and S1 are eliminated due to the fact that the l is placed directly intoflip-flop S2. Accordingly, the contents of the refresh memory at cursoraddress 2-3 are read into the T register. Thus, a code for the characterG is set in the T register. A test is then made to determine whether a 4is in the cursor X counter. Since it is not, the recycle flip-flopremains set. The code for the character F in the ID register is thentransferred to the refresh memory to the position specified in thecursor X counter, namely, position 2-3. The cursor X counter is thenincremented so that the cursor address is 2-4. The code for thecharacter 6 in the T register is then transferred to the ID register.During the third sequence, again, as in all recycles, the state S2 isinitiated first so that the microfunctions appearing during states S0and S] are again eliminated. The contents of the refresh memory ataddress 24, namely, the code for the character H, are read into the Tregister. A test is then made to determine whether the 4 appears in thecursor X counter. Since it does, the recycle flipflop is reset. Thecharacter code for the letter G in the ID register is then transferredto the refresh memory to position 2-4. The cursor X counter is thenincremented causing the address threin to go to 3-1. The character codefor the letter H in the T register is then transferred to the IDregister. (Since this is the last recycle, the H is lost since the H isnot transferred to the refresh memory.)

Since the recycle flip-flop has been reset, the microfunctions of stateS7 of the sequence are caused to be executed recycle S7 END The firstedit which com- EDIT I prises the "Delete Linc instruction is thentermihated by resetting the thereby causing the original cursor addresswhich has been PPP PQ p r of the stored in the temporary cursor store tobe preset into the curzffi f fi g sor X and cursor Y counters. Also theinstruction register is by setting adifferent porreset thereby endingthe edit instruction. tiori of the instruction The Delete Line"instruction causes the line in which the cursor is located to becompletely deleted and each of the lines of characters therebelow aremoved up one line.

As seen in chart IV hereinbelow, the Delete Line instruction The secondedit which forms the second portion of the is performed in two parts.Delete Line instruction is similar to the Clear Line instruction exceptthat during state S0, instead of presetting the tempora- CHART IV l5 rycursor storage to the count presently in the cursor X and cursor Ycounters, the cursor X counter is reset. Thus, the

DELETE LINE INSTRUCTION cursor counter is set to 4-1 and the 2-2 whichis stored in the temporary cursor storage register is placed in thecursor X and cursor Y counter during state S7 of the last sequence ofthe in- A B C D A BC D A BC I) su'uction F; L The Enter Instructioncauses a new character to be placed M N O p A B at the location of thecursor.

Display Prior Display After First Display After to Instruction Part ofInstruction Instruction CHART V Executed ENTER lNSTRUCTlON ABCD ABCD Asseen in Chart IV, the first part of the instruction causes E F G H E R GH the deletion of the second line of the display and each of the P PSucceeding E are copied PP P shquld be Display Prior tolnstructionDisplay After Letter "R that the top line has been copied into thefourth line of the disis Entered play after the first part of theediting instruction. Thus, the

second part of the instruction is a Clear Line instruction which i fromthe cursor and Proceeds to Thus, as seen in Chart V, with the display asshown prior to Posmon instruction and the letter R key on the keyboard22 depressed,

The fi f oflflsll'llctlons first ohhe the letter R is placed in theposition of the cursor with the Delete mstrucuo as fonows: previouscharacter located thereat erased. It should also be 40 noted that thecursor is moved to the next position. g g DESCRIPTION As soon as acharacter key is depressed on the character g FUNCTION keyboard, thecode for the character is placed directly into the ID register 94. Thedepression of the character key also causes the "Enter instruction to beplaced in the instruction register 1 70 which causes the followingsequence of microfunctions in stored tn the temporary th U cursorstorage register, 6 con SI RCX The cursor X counter is SEQUENCE reset tol MICRO- DESCRIPTION S2 INCY The cursor address in the STATE FUNCTIONcursor Y counter is moved so down one line.

S38 READ The memory cycle is $4 lD-T The "R.' in the ID initiated toaccess the r g ster i sent o the T contents of the refresh memoryregister. at the position specified in R RM The R in the T register thecursor X and cursor Y 5 isftlylen sefnt t: the input counter. o e re resmemory.

84A DECY Cursor 1 counter is decre- 85B WRITE F f "R" is hell merited tomove the cursor x 'e tro ly g ftg p ggg up one line. 0

s45 RM-T The contents of the refresh 2:312:2 X memory position that wasaccessed is fed to the T INCX it fiqgypzm gregister.

S5 T-RM The character code in the fgaz gg lr P agf fai' f fs g g sonTEST The testis unconditional memory thereby causing the recycle 55BWRITE The character code at the m zffm'g t r. is read into the refreshthe from m n 9 memory specified by the curas: S6 m S7 op sor X andcursor Y counter.

56A TEST The test is made for the S7 END afg'f f'fg 'zgwas 3:211: 1? 25: [t can therefore be seen that the entering of data is similar to Ycounters. the operation of a typewriter with the cursor moved to the 565INCX 9 tumor is "W next position so that the next character keydepressed causes If cursor mum" the character to be written at theposition of the cursor.

equals 4' pmceed ChTlI FJpsults of a Delete Character instruction areshown in to S7. otherwise CHART VI A B C D A B C D I H L iii L DisplayPrior to Display After Instruction Instruction Executed The sequence ofoperations for the delete character instruction is as follows:

SEQUENCE STATE MICROFUNCTION S C-eCT S2 INCX S38 READ 54A DECX S48 RM-TTEST (for C =4) SSA BLANK-T only ifC 4 S5 T'RM SSB WRITE 86A INCX Il'C4, proceed to S7, otherwise recycle S7 TC-C END EDIT In the DeleteCharacter instruction, the character at the cursor is removed and thenext character placed in its position during the first sequence. In thenext sequences, the remaining characters are moved one position to theleft. In the last sequence, the last character in the line is moved tothe next to last position and the last position is filled with a blankspace.

The results of an Insert Line instruction are shown in Chart VII. Theinsert line instruction also requires two edit tion Executed During thefirst edit sequences, each of the lines from the cursor line down arecopied in the line below. It should be noted that the bottom line islost. The first sequence of operations is, therefore, as follows:

SEQUENCE STATE MICROFUNCTION SI RCX,SET CY T04 S2 DECY 53B READ 84A INCYSSE DECY only if C 4 WRITE 86A INCX (inhibit a carry to CY) 863 TEST(for TCY CY) If TCY CY, proceed to S7, otherwise recycle S7 END EDIT IAs soon as edit 1 of the Insert Line instruction is completed, a ClearLine instruction is initiated. Since the cursor is at 2-] prior to theClear Line instruction, the second line is cleared with the cursorremaining at position 2-l.

It can therefore be seen that a new and improved edit control for avideo display terminal has been provided. The edit control includes aplurality of temporary storage registers to enable the data in therefresh memory to be moved around in order to accomplish instructionswhich are otherwise impossible on existing video display terminalswithout requiring extensive erasing of the character display andconsequent reinsertion of the necessary data.

It can also be seen that the execution of the instructions issubstantially immediate and is carried out during the retrace timebetween each of the horizontal scan lines of the video scan raster.

It should be understood that the instructions which have been describedabove are exemplary only and that the edit control enables various otherinstructions with only a single depression of a key on the keyboardbeing required to execute these instructions.

Without further elaboration, the foregoing will so fully illustrate myinvention that others may, by applying current or future knowledge,readily adapt the same for use under various conditions of service.

What is claimed as the invention is:

I. In a video display terminal having input means for receiving data andinstructions, a refresh memory responsive to said input means, and acathode ray tube, controlled by the contents of said refresh memory,tube for displaying data in accordance with the data and the position ofsaid data in said refresh memory inserted in said refresh memory by saidinput means by providing an alpha-numeric representation of said data ina scan raster comprised of a plurality of parallel scan lines, editingmeans, said editing means being responsive to said input means andcontrolling the data and location of the data in said refresh memory andbeing initiated at the end of each of said scan lines to immediatelyenter said data into said memory and carry out said instructions forchanging the location of data in said memory, said editing means beingoperable only during the time between the successive scan lines on saidcathode ray tube.

2. The video display terminal of claim 1 wherein the periods betweenscan lines are divided into a plurality of intervals.

3. The invention of claim 2 wherein said intervals are defined by asequencing means having a plurality of output lines which aresequentially energized during sequential portions of said intervalbetween said scan raster lines.

4. The invention of claim 3 wherein a plurality of said periods betweenscan lines are required, said sequencing means being operated for onecycle during each of said periods.

5. The invention of claim 3 wherein said sequencing means comprises ashift register and said output lines comprise the output lines of thestages of said shift register.

6. The invention of claim 5 wherein means are provided for inserting anenabling bit into the first stage of said shift register only during afirst cycle, and means for inserting an enabling bit into anintermediate stage of said shift register in subsequent cycles.

7. The invention of claim 6 wherein said enabling bit is shifted fromthe stage in which it is inserted to the next to last stage of the shiftregister in all cycles but the last wherein said enabling bit is alsoshifted into the last stage of said shift register.

8. An edit control for a video display terminal having a memory whichstores the character codes for each character displayed and a characterdisplay which is controlled by said memory to display in alpha-numericform the characters stored in said memory in accordance with thelocation of said character codes in said memory, said edit controlincluding address means comprising a counter for access to said memory,the count of said counter controlling the location in said memory towhich and from which a character code may be transferred, temporarystorage means connected to said address means for storing the address insaid address means at the start of an editing operation, temporarycharacter code storage means, and means for initiating the transfer ofdata between said temporary character code storage means and saidmemory, said means for initiating transfer of data controlling the countof said counter so that the characters in said display may be entered,removed, or moved in accordance with the entering, removing, or movingof said character codes in said memory.

9. The edit control of claim 8 and further including a sequence means,said sequence means being connected to said means for initiatingtransfer of data so that a plurality of said data transfers may besequentially initiated.

10. The edit control of claim 9 and further including an instructionregister for storing an instruction until it has been executed by saidedit control, said means for initiating transfer of data also beingresponsive to said instruction to provide a predetermined set oftransfers in accordance with the instruction in said instructionregister.

ii, The edit control of claim 8 wherein said sequencing means comprisesa shift register, said shift register having an output line for eachstage thereof, said output lines enabling said means for initiatingtransfer of data.

12. The edit control of claim It wherein said means for initiatingtransfer of data is responsive to said instruction and said plurality ofoutput lines to provide sequences of data transfers in accordance withthe signals provided on said output lines.

13. An edit control responsive to instructions for manipulating thecontents of the display of a video display terminal having a memorywhich stores the character codes for each character display position anda character display which is controlled by said memory, and addressmeans for accessing said memory, said edit control further includingmeans for generating a plurality of sequence states responsive toinstructions received by said edit control, and means responsive to afirst portion of said sequence states to execute at least onemicroinstruction, to a second portion of said sequence states to executeat least one microinstruction, and to a third portion of said sequencestates to execute at least one microinstruction, said means forgenerating a plurality of sequence states generating said first andsecond portion of said sequence states upon receipt by said edit controlof an instruction, test means responsive to the address means and saidmemory to detect a predetermined condition to enable the generation ofsaid third portion of said sequence states otherwise said testing meansenables the regeneration of said second portion of said sequence statesuntil said predetermined condition is detected, and transfer means, saidmicroinstructions controlling said address means and said transfer meansfor entering, removing and moving character codes in said memory.

1. In a video display terminal having input means for receiving data andinstructions, a refresh memory responsive to said input means, and acathode ray tube, controlled by the contents of said refresh memory,tube for displaying data in accordance with the data and the position ofsaid data in said refresh memory inserted in said refresh memory by saidinput means by providing an alpha-numeric representation of said data ina scan raster comprised of a plurality of parallel scan lines, editingmeans, said editing means being responsive to said input means andcontrolling the data and location of the data in said refresh memory andbeing initiated at the end of each of said scan lines to immediatelyenter said data into said memory and carry out said instructions forchanging the location of data in said memory, said editing means beingoperable only during the time between the successive scan lines on saidcathode ray tube.
 2. The video display terminal of claim 1 wherein theperiods between scan lines are divided into a plurality of intervals. 3.The invention of claim 2 wherein said intervals are defined by asequencing means having a plurality of output lines which aresequentially energized during sequential portions of said intervalbetween said scan raster lines.
 4. The invention of claim 3 wherein aplurality of said periods between scan lines are required, saidsequencing means being operated for one cycle during each of saidperiods.
 5. The invention of claim 3 wherein said sequencing meanscomprises a shift register and said output lines comprise the outputlines of the stages of said shift register.
 6. The invention of claim 5wherein means are provided for inserting an enabling bit into the firststage of said shift register only during a first cycle, and means forinserting an enabling bit into an intermediate stage of said shiftregister in subsequent cycles.
 7. The invention of claim 6 wherein saidenabling bit is shifted from the stage in which it is inserted to thenext to last stage of the shift register in all cycles but the lastwherein said enabling bit is also shifted into the last stage of saidshift register.
 8. An edit control for a video display terminal having amemory which stores the character codes for each character displayed anda character display which is controlled by said memory to display inalpha-numeric form the characters stored in said memory in accordancewith the location of said character codes in said memory, said editcontrol including address means comprising a counter for access to saidmemory, the count of said counter controlling the location in saidmemory to which and from which a character code may be transferred,temporary storage means connected to said address means for storing theaddress in said address means at the start of an editing operation,temporary character code storage means, and means for initiating thetransfer of data between said temporary character code storage means andsaid memory, said means for initiating transfer of data controlling thecount of said counter so that the characters in said display may beentered, removed, or moved in accordance with the entering, removing, ormoving of said character codes in said memory.
 9. The edit control ofclaim 8 and further including a sequence means, said sequence meansbeing connected to said means for initiating transfer of data so that aplurality of said data transfers may be sequentially initiated.
 10. Theedit control of claim 9 and further including an instruction registerfor storing an instruction until it has been executed by said editcontrol, said means for initiating transfer of data also beingresponsive to said instruction to provide a predetermined set oftransfers in accordance with the instruction in said instructionregister.
 11. The edit control of claim 8 wherein said sequencing meanscomprises a shift register, said shift register having an output linefor each stage thereof, said output lines enabling said means forinitiating transfer of data.
 12. The edit control of claim 11 whereinsaid means for initiating transfer of data is responsive to saidinstruction and said plurality of output lines to provide sequences ofdata transfers in accordance with the signals provided on said outputlines.
 13. An edit control responsive to instructions for manipulatingthe contents of the display of a video display terminal having a memorywhich stores the character codes for each character display position anda character display which is controlled by said memory, and addressmeans for accessing said memory, said edit control further includingmeans for generating a plurality of sequence states responsive toinstructions received by said edit control, and means responsive to afirst portion of said sequence states to execute at least onemicroinstruction, to a second portion of said sequence states to executeat least one microinstruction, and to a third portion of said sequencestates to execute at least one microinstruction, said means forgenerating a plurality of sequence states generating said first andsecond portion of said sequence states upon receipt by said edit controlof an instruction, test means responsive to the address means and saidmemory to detect a predetermined condition to enable the generation ofsaid third portion of said sequence states otherwise said testing meansenables the regeneration of said second portion of said sequence statesuntil said predetermined condition is detected, and transfer means, saidmicroinstructions controlling said address means and said transfer meansfor entering, removing and moving character codes in said memory.